FlexRay is a network communication protocol developed by the FlexRay consortium for controlling on board systems in self-driving cars. It was developed as a faster and more reliable protocol than CAN and TTP, but at the same time it is also more expensive. The FlexRay consortium dissolved in 2009, but the information still can be downloaded from the FlexRay homepage. The FlexRay standard currently is being converted to an ISO standard

The characteristics of FlexRay

  • High data rates (up to 10 Mbps)
  • Time and event triggering behavior
  • Fault tolerance

FlexRay – The Consortium

The FlexRay consortium consisted of the following main members:

  • Freescale Semiconductor
  • Robert Bosch GmbH
  • NXP Semiconductors
  • BMW AG
  • Volkswagen AG
  • Daimler AG
  • General Motors

In addition, the consortium had premium and extraordinary members. In September 2009, there were 28 premium members and over 60 extraordinary members. The consortium dissolved at the end of 2009.

FlexRay – Use

The first product series equipped with FlexRay was produced at the end of 2006 in the BMW X5. It provided a new and quickly adapting damping system. In 2008, FlexRay was integrated fully in the new BMW 7 series (F01), the world’s first production car completely using the FlexRay system.


  • Audi A6
  • Audi A8
  • Bentley Mulsanne
  • BMW X5
  • BMW 7 Series
  • BMW 5 Series Gran Turismo
  • BMW 5 Series
  • Rolls-Royce Ghost


The FlexRay system is composed of a bus and a processor (electronic control unit (ECU)). Each ECU has an integrated independent clock. The time deviation from the reference clock may not exceed 0.15 %, so that the difference between the slowest and the fastest clock in the system does not exceed 0.3 %. As such, when ECU-s is the transmitter and ECU-r is the receiver, 300 cycles of the transmitter always will result in 299 to 301 cycles at the receiver. The clocks are synchronized continuously to ensure that no problems are caused by this.


The bus is always described by one ECU only. Every bit which is to be sent to the bus must be held for eight time cycles. The receiver keeps a buffer for the last five samples and it uses most of the last five samples as the input signal.

Sample Bits

The value of a bit is found near the 8-bit region. The errors are shifted into the extreme cycles, and the clock is synchronized often enough, so that the deviation is only small. (The deviation is smaller than one cycle per 300 cycles. During the transmission, the clock is synchronized more frequently, i.e. more often than all 300 cycles.)


The entire communication takes place with the aid of frames. The message contains bytes {x0, x1,..., xm-1}, as shown below:

  • Transmission start signal (TSS) - bit 0
  • Frame start signal (FSS) - bit 1
  • M times:
    • Byte start signal 0 (BSS0) - bit 1
    • Byte start signal 1 (BSS1) - bit 0
    • 0th bit of the ith cycle
    • 1st bit of the ith cycle
    • 2nd bit of the ith cycle
    • ...
    • 7th bit of the ith cycle
  • Frame end signal (FES) - bit 0
  • Transmission end signal (TES) - bit 1

Clock Synchronization

The clocks are resynchronized when the signal changes from 1 to 0, i.e. when the receiver was either in the inactive state or expected BSS1. The clock is synchronized when the transmission starts. When synchronization of the selected signal has been completed, small transmission errors can change the synchronization by not more than one cycle. As there are max. 88 cycles between synchronizations BSS1, 8 bits of the last byte, FES and TES - 11 bits of 8 cycles each) and the clock deviation does not exceed 1 per 300 cycles, the deviation does not change by more than one cycle. Small transmission errors during reception only concern the boundary bytes. As such, in the worst case, the bits in the middle are correct, so that the entire value is correct.This is an example for an unfavorable case: an error during synchronization, a lost cycle because of clock deviations and an error in the transmission.Errors which occur in this example:

  • The synchronization is delayed by one cycle because of the single bit error during synchronization
  • The receiver clock was slower than the transmitter clock, so that the receiver misses one cycle (marked with X). Because of the rules for the max. clock deviation, this will not happen again before the next synchronization
  • Because of the single bit error during the transmission, one bit near the result is selected incorrectly.

In spite of these many errors, the message was received correctly.

The green cells are sampling points.

Flex Ray